PIL testing of the Optical On-Board Image Processing Solution for EO-ALERT

PIL testing of the Optical On-board Image Processing Solution for EO-ALERT

F. Membibre, A. Latorre, A. Ramos, J. I. Bravo, R. Hinz, A. Morón, M. Kerr

DEIMOS Space S.L.U., Tres Cantos – Madrid, Spain, Email:

{francisco.membibre, antonio.latorre, alexis.ramos, juan-ignacio.bravo, robert.hinz, alvaro.moron, murray.kerr}@deimos-space.com

Abstract

EO-ALERT (http://eo-alert-h2020.eu/) is a European Commission H2020 project coordinated by DEIMOS Space, whose main objective is to obtain Earth Observation products with very low latency (<5 minutes) using global communications links. To carry it out, the satellite sensor data are processed on-board the flight segment to obtain the target products, which are alerts in our applications (ship detection and extreme weather). This on-board processing is achieved through efficient use of novel and advanced COTS technologies, including spin-in from other sectors, such as advanced Multi-Processor and FPGA (Zynq™ UltraScale+™ MPSoC from Xilinx®), multi-board reconfiguration, use of COTS elements for advanced processing or rapid-development (Linux OS, SDSoC™ from Xilinx® or OpenCV libraries) and high-speed interfaces.

In order to program this COTS device from a global perspective in high level languages, the platform concept has been used. It is based on the block design of the FPGA and the custom Linux created with the Petalinux tool. Once the platform is ready, the new tools for programming Xilinx® COTS allow using all board resources such as IP cores in the FPGA for hardware acceleration or the use of parallel processing frameworks like OpenMP to fork the data between the 4 available cores to increase the performance.

To process the sensor images and obtain the target products, artificial intelligence (AI) and machine learning (ML) algorithms developed in the project are implemented by migrating them to the target Hardware, taking into account the most efficient implementation on the system multi-core (4 A53 ARM® cores) or FPGA. The development includes the use of rapid prototyping tools to produce optimized hardware IP blocks and SW libraries.

In the implementation and verification phase, a PIL (Processor-In-the-Loop) testbench is created. The objective of the test bench is to have a multi-board breadboard representative of the final architecture, in which to validate the design and its performance. The execution times are measured in the PIL platform, obtaining at the present moment results within the requirements (<5 minutes) established in the project.

For that, the HW architecture allows a master-slave configuration, to be used for this on-board processing, thus reducing the total latency of the product generation or cover more area. On each board the processing takes advantage of the board’s resources (multi-core, FPGA) to obtain the processed products and alerts, which are centralised in the master processing board.

In addition, the results are highly significative due to the evaluation of the resulting processing system is performed experimentally using real Earth Observation data from a reference-image database, corresponding to the DEIMOS-2 VHR optical satellite and the multispectral SEVIRI instrument on the MSG satellite. Ground truth information from multiple sources is used in the verification phase. Furthermore, the performance of the initial algorithms is compared with those obtained in the Hardware, thus obtaining an evaluation of the effect of the Hardware implementation.